Baud rate (i.e., sampling at data rate) phase detectors are used widely in high speed serial links (e.g., links with data rates greater than 8 Gb/s) due to better power, less complexity and area usage compared to oversampling based timing recovery. However, the commonly used timing function, which is generally referred to as the Mueller-Muller phase detector based timing function, may require strong pre-emphasis to be applied on the signal either in the transmitter or the receiver, to drive the Inter-Symbol Interference (ISI) from the first pre-cursor to zero thereby providing a strong timing lock. Here, timing lock refers to positioning the sampling clock edge in a way which affords maximum tolerance to input jitter.
The left-right centering (i.e., horizontal centering) of the sampling clock edge position within the received data eye is a strong function of the pre-emphasis. For high loss channels, where de-emphasis may be required in addition to pre-emphasis, the resulting data eye margins may be limited by the maximum boost (i.e., combination of pre-emphasis and de-emphasis) that can be applied and by the available gain of the receiver since high gain and high bandwidth are difficult to achieve in highly scaled CMOS processes. Therefore, a baud rate sampling method that does not require as much pre-emphasis and that can tolerate a non-zero first precursor ISI and not require additional gain, is highly desirable.